1. Field of the Invention
The present invention relates to user-programmable interconnect architectures employing antifuse elements. More particularly, the present invention relates to such architectures adapted to permit the use of leaky antifuse elements.
2. The Prior Art
In some user-programmable interconnect architectures incorporating logic function circuits, such as field-programmable gate array (FPGA) circuits, all unrouted inputs to the logic function circuits are tied to either a V.sub.CC conductor or a ground conductor during the programming process. In general, existing products, such as those manufactured by Actel Corporation of Sunnyvale, Calif., employ a single continuous V.sub.CC or ground tie-off track for every group (called a routing channel) of interconnect conductors. During normal circuit operation, the V.sub.CC and ground tie-off tracks are connected to V.sub.CC and ground potentials, respectively. These lines in turn pass V.sub.CC and ground potentials to the selected inputs through selectively programmed antifuses. These tie-off tracks are also used to tie unused general interconnect conductor segments to a fixed voltage potential, usually ground.
In some prior art FPGA devices, notably the ACT2 and ACT3 families of products manufactured by Actel, the antifuses which are used to tie off unrouted inputs are programmed by taking the horizontal tie-off track (V.sub.CC /ground) up to the programming voltage (V.sub.PP) while grounding the vertical track, usually a function circuit input. For a 10K gate die, as many as 800 inputs may be tied to a single VCC or ground track. All other horizontal tracks and module inputs are maintained at a voltage of V.sub.PP /2 during this programming step so as to prevent inadvertent programming of a wrong antifuse.
This architecture presents several potential problems, especially when "leaky" antifuses, such as antifuses employing amorphous silicon antifuse material layers, are employed in the design. Changes in the antifuse processing method, or normal variances in a single antifuse process, can result in a wide range of leakage currents through the many unprogrammed antifuses, during programming of a single antifuse. If the individual leakage currents are high (e.g.&gt;10 nA) a significant and undesirable leakage current must be supplied from the V.sub.PP programming voltage source, in addition to the expected programming current.
The highest leakage current occurs on a V.sub.CC /ground tie-off track as the last antifuse on that line is being programmed. Each of the approximately 800 previously programmed input tie-offs crosses approximately 35 horizontal general interconnect tracks, which are biased at a voltage of V.sub.PP /2. This can result in up to 28,000 antifuses contributing leakage current, which must be supplied from the V.sub.PP programming voltage source. Depending on the leakage of a specific antifuse technology, supplying the leakage current from the programming voltage source may be difficult or impossible.
The aforementioned leakage characteristics of the antifuses may also cause an incorrect antifuse to be programmed. Consider a full length horizontal track which is precharges to V.sub.PP /2 prior to a programming cycle and either left floating or weakly held at V.sub.PP /2 during the programming cycle. While programming antifuses on the V.sub.CC /ground track, as many as 800 unprogrammed antifuses will be sourcing leakage current to the horizontal track while only a single antifuse will be sinking current from the track. The horizontal track voltage may rise sufficiently to erroneously program the single antifuse sinking the current.
It is therefore an object of the present invention to provide an antifuse-based interconnect architecture which overcomes the shortcomings of the prior art.
Another object of the invention is to provide a viable interconnect architecture tolerant to programmable elements with poor electrical characteristics.
It is a further object of the invention to provide an interconnect architecture which maximizes correct programming of intended antifuses.
Another object of the invention is to provide an interconnect architecture which allows the use of different types of programmable elements with poor I-V charcteristics and good RC electrical characteristics, and allows use of inferior programmable elements.
Another objective is to provide an interconnect architecture which allows the use of different types of programmable elements which are simpler to fabricate.